There is a single-slope AD converter as one of analog-digital converters (AD converters) that convert analog signals to digital signals (see Non-Patent Literatures 1, 2, for example). The single-slope AD converter is an AD converter having a small area and low power consumption, but has the drawback of slow conversion speed. Therefore, the use of the single-slope AD converter has been limited to an image sensor, and so on conventionally.
FIG. 9A is a diagram illustrating a configuration example of a single-slope AD converter, and FIG. 9B is a view illustrating a principle of operation of the single-slope AD converter. The single-slope AD converter illustrated in FIG. 9A includes: a track and hold (TH) circuit 91; a comparator 92; a ramp circuit (RAMP) 93; and a time to digital converter (TDC) 94.
The track and hold circuit 91 includes: a switch SW91 that is on/off controlled by a clock signal CK and transmits an analog input signal VIN; and a holding capacitance C91 that holds the analog input signal VIN transmitted via the switch SW91. The comparator 92 compares an input potential Vsam and a reference potential Vref to output a signal S91 according to a result of the comparison. The input potential Vsam is a potential according to the analog input signal VIN input and held by the track and hold circuit 91, and is reduced at a constant speed by the ramp circuit 93 during a comparing period in an AD conversion operation.
The ramp circuit 93 includes: a switch SW92; and a current source IS91 to be connected to an input node of the input potential Vsam via the switch SW92. At the time of a comparing operation of AD conversion processing, the switch SW92 is turned on, the current source IS91 is connected to the input node of the input potential Vsam, and the ramp circuit 93 reduces the input potential Vsam at a constant speed. The time to digital converter 94 converts a time difference indicated by the signal S91 output from the comparator 92 to a digital value to output it as a digital signal DOUT.
In the single-slope AD converter illustrated in FIG. 9A, as illustrated in FIG. 9B as one example, the input analog input signal VIN is sampled by the track and hold circuit 91 at times T91 to T92 at which the clock signal OK is at a high level. After the analog input signal VIN is sampled by the track and hold circuit 91, the comparing operation of the AD conversion processing is started from a time T93 and the ramp circuit 93 reduces the input potential Vsam according to the sampled analog input signal VIN at a constant speed.
In the comparing operation of the AD conversion processing, the signal S91 to be output from the comparator 92 when the ramp circuit 93 starts to reduce the input potential Vsam according to the analog input signal VIN (when the comparing operation is started) is at a high level because the input potential Vsam is higher than the reference potential Vref (time T93). Thereafter, when the input potential Vsam is reduced to be equal to the reference potential Vref, the signal S91 to be output from the comparator 92 is brought to a low level (time T94).
A time period taken until the input potential Vsam becomes equal to the reference potential Vref after the ramp circuit 93 starts to reduce the input potential Vsam, namely a time tsam of the times T93 to T94 at which the signal S91 to be output from the comparator 92 is at a high level is converted to a digital value by the time to digital converter 94. The time tsam is proportional to a potential Vs according to the analog input signal VIN held by the track and hold circuit 91 when the comparing operation of the AD conversion processing is started, and thus the output of the time to digital converter 94 becomes an AD conversion result of the analog input signal VIN.
In this manner, a digital value DOUT2 obtained by the AD conversion of the analog input signal VIN sampled at the times T91 to T92 is output as the digital signal DOUT. Incidentally, a digital value DOUT1 is an AD conversion result of the analog input signal VIN sampled one before.
When the number of bits of the time to digital converter 94 is set to n (an output value is 0 to (2n−1)) and a time resolution is set to Δt in the single-slope AD converter illustrated in FIG. 9A, the maximum value tsam(max) of the time tsam is expressed as 2nΔt. When fabrication of a single-slope AD converter that converts to a 10-bit digital signal is considered, for example, the time tsam(max) becomes 102.4 ns in the case of the time resolution Δt being 100 ps. A sampling period Ts of an input signal in the AD converter is substantially equal to the sum of a track period ttr and the time tsam(max), and thus a sampling frequency of the AD converter becomes 10 MHz or less.
In this manner, the single-slope AD converter has had difficulty in achieving speeding up because a conversion time increases exponentially with respect to the accuracy (bit number) in spite of a small number of components, a small circuit area, and low power consumption.